IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 103
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 103 of 422
- Download datasheet (6Mb)
Chapter 6: Performing SignalTap II Logic Analysis
SignalTap II Example Designs
Specifying the Nodes to Analyze
© June 2010 Altera Corporation
Table 6–1. Parameters for the Pulse Generator Blocks
9. Select the Simulink Sinks library. Drag and drop a Terminator block near to the
To add SignalTap II Node blocks to the signals (also called nodes) that you want
to analyze (in this tutorial they are the output of each AND gate and the output of the
incrementer), follow these steps:
1. Open the AltLab library in the Simulink Library Browser. Drag a SignalTap II
Parameter
Pulse type
Time
Amplitude
Period
Pulse Width
Phase delay
Interpret vector parameters as 1-D
OR_Gate block and connect it to this block.
Node block into your design. Position the block so that it is on top of the
connection line between the AND_Gate1 block and the OR_Gate block
(Figure
1
If you position the block with this method, the Simulink software inserts
the block and joins connection lines on both sides.
6–4).
Preliminary
Value
Time based
Use Simulation time
1
2
50
0
On
DSP Builder Standard Blockset User Guide
6–5
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: