IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 48

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–4
Bit Width Design Rule
Data Width Propagation
DSP Builder Standard Blockset User Guide
f
■
In VHDL, DSP Builder types the signals as STD_LOGIC_VECTOR.
For example, DSP Builder represents the 4-bit binary number 1101 as:
If you change the location of the binary point to 11.01, that is, two bits on the left side
of the binary point and two bits on the right side, DSP Builder represents the numbers
as:
From a system-level analysis point of view, multiplying a number by –0.75 or –3 is
very different, especially when looking at the bit width growth. In the first case, the
multiplier output bus grows on the most significant bit (MSB), in the second case, the
multiplier output bus grows on the least significant bit (LSB).
In both cases, the binary numbers are identical. However, the location of the binary
point affects how a simulator formats the representation of the signal. For complex
systems, you can adjust the binary point location to define the signal range and the
area of interest.
For more information about number systems, refer to
Systems.
You must specify the bit width at the source of the datapath. DSP Builder propagates
this bit width from the source to the destination through all intermediate blocks. Some
intermediate DSP Builder blocks must have a bit width specified, while others have
specific bit width growth rules which are described in the documentation for each
block.
Some blocks which allow bit widths to be specified optionally, have an Inferred
type setting that allows a growth rule to be used. For example, in the amplitude
modulation tutorial design
blocks have a bit width of 16. Therefore, a bit width of 16 is automatically assigned to
the intermediate Delay block.
You can specify the bit width of many Altera blocks in the Simulink design. However,
you do not need to specify the bit width for all blocks. If you do not specify explicitly
the bit width, DSP Builder assigns a bit width during the Simulink-to-VHDL
conversion by propagating the bit width from the source of a datapath to its
destination.
Some intermediate DSP Builder blocks must have a specified bit width, while others
have specific bit width growth rules that the documentation for each block describes.
Some blocks, which allow bit widths to be specified optionally, allow use of a growth
rule—the Inferred type setting.
[].[number of bits]—represents the number of bits to the right of the binary point.
Simulink
VHDL
Simulink
VHDL
This signed fraction is interpreted as –0.75
This signed STD_LOGIC_VECTOR is interpreted as –3
This signed integer is interpreted as –3
This signed STD_LOGIC_VECTOR is interpreted as –3
(Chapter 2, Getting
Preliminary
Started) the SinIn and SinDelay
AN 83: Binary Numbering
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Bit Width Design Rule