IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 24

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–2
Figure 2–1. System-Level Design Flow
DSP Builder Standard Blockset User Guide
Figure 2–1
The design flow involves the following steps:
1. Use the MathWorks software to create a model with a combination of Simulink
2. Include a Clock block from the DSP Builder AltLab library to specify the base
and DSP Builder blocks.
1
clock for your design, which must have a period greater than 1ps but less than 2.1
ms.
1
Separate The DSP Builder blocks in your design from the Simulink blocks
by Input and Output blocks from the DSP Builder IO and Bus library.
If no base clock exists in your design, DSP Builder creates a default clock
with a 20ns real-world period and a Simulink sample time of 1. You can
derive additional clocks from the base clock by adding Clock_Derived
blocks.
shows the system-level design flow using DSP Builder.
Preliminary
© June 2010 Altera Corporation
Chapter 2: Getting Started
Design Flow