IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 49
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
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Chapter 3: Design Rules and Procedures
Bit Width Design Rule
Figure 3–2. 3-Tap FIR Filter
Figure 3–3. 3-Tap FIR Filter in Quartus II RTL View
© June 2010 Altera Corporation
Figure 3–2
The fir3tapsub.mdl design is a 3-tap finite impulse response (FIR) filter and has the
following attributes:
■
■
■
■
Figure 3–3
Compiler.
Tapped Delay Line
The bit width propagation mechanism starts at the source of the datapath, in this case
at the Input block, which is an 8-bit input bus. This bus feeds the register U0, which
feeds U1, which feeds U2. DSP Builder propagates the 8-bit bus in this register chain
where each register is eight bits wide
The input data signal is an 8-bit signed integer bus
The output data signal is a 20-bit signed integer bus
Three Delay blocks build the tapped delay line
The coefficient values are {1.0000, -5.0000, 1.0000}, a Gain block performs the
coefficient multiplication
illustrates bit-width propagation.
shows the RTL representation of fir3tapsub.mdl created by Signal
Preliminary
(Figure
3–4).
DSP Builder Standard Blockset User Guide
3–5
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