IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 200

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1–10
Table 1–12. HIL Block Parameters, Page 1 (Part 2 of 2)
Table 1–13. HIL Block Parameters, Page 2
Figure 1–2. Example With the HIL Block
DSP Builder Standard Blockset Libraries
Assert “Sclr” before
starting the simulation
Note to
(1) The record size is 32×1024×1024, which is the product of (packet size) × (burst length) while the packet size is the larger of the total input data
FPGA device
Compile with Quartus II
JTAG Cable
Device in chain
Scan JTAG
Configure FPGA
Transcript window
width and the total output data width. For example, for a packet size of 1024 bits, set the burst length to 32×1024. However, due to the
limitations of the JTAG interface, the optimal record size is between 1 to 2 MBPS (depending on the host computer, USB driver and cables).
Hence, setting a bigger burst size might not give significant speed up.
Table
Name
Name
1–12:
1
1
The HIL block needs recompilation if you change the Quartus II project, clock pin, or
any of the exported ports.
Table 1–13
Figure 1–2
Refer to the “Using Hardware in the Loop” chapter in the
User Guide
On or Off
device name
cable name
device location The required entry for the location of the device.
Value
Value
—
—
—
—
shows the parameters specified in page 2 of the HIL dialog box.
shows an example with the HIL block.
section in volume 2 of the DSP Builder Handbook.
When on, asserts the synchronous clear signal before the simulation starts.
The FPGA device.
Click to compile the HIL block with the Quartus II software.
The JTAG cable.
Click to scan the JTAG interface for all JTAG cables attached to the system
(including any remote computers) and the devices on each JTAG cable. The
available cable names and device names are loaded into the JTAG Cable and
Device in chain list boxes.
Click to configure the FPGA.
Displays the progress of the compilation.
Preliminary
Description
Description
DSP Builder Standard Blockset
© June 2010 Altera Corporation
HIL (Hardware in the Loop)
Chapter 1: AltLab Library