IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 72

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–28
Figure 3–26. Preserve Registers Assignment in the Quartus II Assignment Editor
DSP Builder Standard Blockset User Guide
These assignments prevent merging of the registers. If you change the length of the
delay, the assignments are no longer valid. However, you can edit the To field of the
assignment and use a regular expression that is still valid if the entity name changes
due to a parameter change: Replace the eight alphanumeric characters following the
GN in the block entity name with .{8}, which is a regular expression that matches any
eight characters. The targets of the assignments then become:
If you want the assignment to apply to the whole block, not just the specific nodes,
you can use the following code:
Figure 3–26
This type of assignment can be useful for a complicated block that contains many
registers when you want the assignment to apply to all of the registers.
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay|alt_dspbuil
der_SDelay:Delay1i|DelayLine
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay1|alt_dspbui
lder_SDelay:Delay1i|DelayLine
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay
my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay1
shows this example in the Quartus II Assignment Editor.
Preliminary
Making Quartus II Assignments to Block Entity Names
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation