IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 345

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Dual-Clock FIFO
Table 9–7. Dual-Clock FIFO Block Inputs and Outputs (Part 2 of 2)
Table 9–8. Dual-Clock FIFO Block Parameters
© June 2010 Altera Corporation
wrfull
wrempty
wrusedw
Number of Words in the FIFO Integer
Input Bus Type
[number of bits].[]
[].[number of bits]
Memory Block Type
Use Base Clock for Read Side On or Off
Read-Side Clock
Use Base Clock for Write
Side
Write-Side Clock
Use Read-Side Synchronized
EMPTY Port
Use Read-Side Synchronized
FULL Port
Use Read-Side Synchronized
USEDW Port
Use Write-Side Synchronized
EMPTY Port
Use Write-Side Synchronized
EMPTY Port
Use Write-Side Synchronized
USEDW Port
Use Asynchronous Clear Port On or Off
Register Output
Implement FIFO with logic
Cells Only
Use Show-Ahead Mode of
Read Request
Signal
Name
Output
Output
Output
Direction
Table 9–8
Optional output synchronized to the write clock. Indicates that the FIFO buffer is full and
disables the wrreq port.
Optional output synchronized to the write clock. Indicates that the FIFO buffer is empty and
disables the rdreq port.
Optional output synchronized to the write clock. Indicates the number of words that are in the
FIFO buffer.
(Parameterizable)
Signed Integer,
Unsigned Integer,
Signed Fractional
>= 0
(Parameterizable)
>= 0
(Parameterizable)
AUTO, M512, M4K,
M9K, MLAB, M144K
User defined
On or Off
User defined
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
shows the Dual-Clock FIFO block parameters.
Value
Specify the FIFO depth
The bus type format.
Specify the number of bits stored on the left side of the binary point.
Specify the number of bits to the right of the binary point. This option
applies only to signed fractional formats.
The FPGA RAM type. Some memory types are not available for all
device types.
Turn on to use the base clock signal for the read-side clock.
Specify the read-side clock signal when not using the base clock.
Turn on to use the base clock signal for the write-side clock.
Specify the write-side clock signal when not using the base clock.
Turn on to use the read-side empty port (rdempty).
Turn on to use the read-side full port (rdfull).
Turn on to use the read-side words port (rdusedw).
Turn on to use the write-side empty port (wrempty).
Turn on to use the write-side empty port (wrfull).
Turn on to use the write-side words port (wrusedw).
Turn on to use the asynchronous clear port (aclr).
Turn on to register the output ports. This mode is faster but larger.
Turn on to implement the FIFO buffer with logic cells only.
Turn on to use the show-ahead mode of read-request.
Preliminary
Description
Description
DSP Builder Standard Blockset Libraries
9–5