IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 67

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Adding Quartus II Constraints
Adding Quartus II Constraints
© June 2010 Altera Corporation
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Figure 3–21. Adding Comments to a Block
DSP Builder includes the comment text next to the instantiation of the block in the
generated HDL.
You can set Quartus II global project assignments in your Simulink model by adding
Quartus II Global Project Assignment blocks from the AltLab library. Each
block sets a single global assignment but you can use multiple blocks for multiple
assignments. You can use these assignments to set Quartus II compilation directives,
such as target device or timing requirements.
For a description of the Quartus II Global Project Assignment block, refer
to the
You can add additional Quartus II assignments or constraints that are not supported
in DSP Builder by creating a Tcl script in your design directory. Any file named <model
name>_add_user.tcl is automatically sourced when you run Signal Compiler.
The Tcl file can include any number of Quartus II assignments with the syntax:
For detailed information about Quartus II assignments, refer to the
File Reference
set_global_assignment -name <assignment> <value>
DSP Builder Reference
Manual.
Manual.
Preliminary
DSP Builder Standard Blockset User Guide
Quartus II Settings
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