IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 311

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
AltBus
Figure 6–1. Floating-Point Conversion
Figure 6–2. Internal Format Conversion
© June 2010 Altera Corporation
Figure 6–2
signed binary fractional format to a 4-bit bus with a [2].[2] signed binary fractional
format.
In VHDL, this results in extracting a 4-bit bus (AltBus(3 DOWNTO 0)) from a 20-bit
bus (AltBus(19 DOWNTO 0)) with the assignment:
AltBus3(3 DOWNTO 0)) AltBus(11 DOWNTO 8))
illustrates the usage of AltBus to convert a 20-bit bus with a ([10].[10])
Preliminary
DSP Builder Standard Blockset Libraries
6–3