IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 79
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 79 of 422
- Download datasheet (6Mb)
Chapter 4: Using MegaCore Functions
MegaCore Function Design Example
© June 2010 Altera Corporation
Table 4–3. Parameters for the Constant Blocks
10. Repeat Step
11. Add a Single Pulse block (from the Gate & Control library in the Altera DSP
12. Use the Block Parameters dialog box to set the parameters
Table 4–4. Parameters for the Single Pulse Block
13. Add an Output block (from the IO & Bus library in the Altera DSP Builder
14. Use the Block Parameters dialog box to set the parameters
Table 4–5. Parameters for the Output Block
15. Add a Scope block (from the Simulink Sinks library). Use the ‘Scope’ Parameters
16. Connect the Scope block to the Input and Output blocks to monitor the source
Parameter
Constant Value
Bus Type
[Number of Bits].[]
Rounding Mode
Saturation Mode
Specify Clock
Parameter
Signal Generation Type
Delay
Specify Clock
Parameter
Bus Type
[number of bits].[]
External Type
Builder Blockset) and connect it to the reset_n pin on the my_fir_compiler
block.
Blockset) to your design and connect it to the ast_source_data pin on the
my_fir_compiler block.
page
dialog box to configure the Scope block as a 2-input scope.
noise data and the filtered output.
Figure 4–4
4–7).
shows how your model looks.
9
for the Constant1 block.
Preliminary
Constant
1
Single Bit
–
Truncate
Wrap
Off
Value
Step Up
50
Off
Value
Signed Integer
18
Inferred
DSP Builder Standard Blockset User Guide
Value
(Table
(Table 4–5 on
Constant1
0
Signed Integer
2
Truncate
Wrap
Off
4–4).
4–7
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: