IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 128

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–20
Avalon-ST Interface
DSP Builder Standard Blockset User Guide
All DSP MegaCore functions in the DSP Builder MegaCore Functions library have
interfaces that comply with the
multiple MegaCore functions easily because they use a common interface. This
section summarizes the features of the Avalon-ST interface.
The
interface and a sink interface. The interface indicates the integrity of the data by a feed
forward signal, valid. The specification also defines how the MegaCore functions
may stall other blocks (backpressure) or regulate the rate at which you provide data
with a feedback sideband signal, ready.
You can configure the DSP Builder Avalon-ST Source and Avalon-ST Sink
blocks with a ready latency of 0 or 1. The ready latency is the number of cycles that a
source must wait after a sink asserts ready so that a data transfer is possible. The
source interface provides valid data at the earliest time possible, and it holds that data
until sink asserts ready. The ready signal notifies the source interface that it has
sampled the data on that clock cycle.
For the ready_latency = 0 mode,
the source interface valid signal and the sink interface ready signal.
Figure 7–12. Avalon-ST Interface Timing for ready-latency=0
On cycle one, the source provides data and asserts valid even though the sink is not
ready. The source waits until cycle two and the sink acknowledges that it samples the
data by asserting ready. On cycle three, the source happens to provide data on the
same cycle that the sink is ready to receive it and so the transfer occurs immediately.
On the fourth cycle, the sink is ready but because the source does not provide any
valid data, the data bus is not sampled.
A beat is the transfer of one unit of data between a source and sink interface. This unit
of data may consist of one or more symbols, so it can support modules that convey
more than one piece of information on each valid cycle. Some modules have parallel
input interfaces and other instances require serial input interfaces. For example, when
conveying an in-phase and quadrature component on the same clock cycle. The choice
depends on the algorithm, optimization technique, and throughput requirements.
Avalon Interface Specifications
Preliminary
Figure 7–12
Avalon Interface
define how to convey data between a source
shows the interaction that occurs between
Specifications. You can combine
Chapter 7: Using the Interfaces Library
© June 2010 Altera Corporation
Avalon-ST Interface