IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 174

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

12–6
Design Example
DSP Builder Standard Blockset User Guide
1
These statements specify the relative path to the directory where to locate the .mdl file
and where to search for directories containing further .ipx files. The ** means search
recursively, and the final * locates all identifiable elements there.
You can combine all the search paths into a single .ipx file. For example:
You can also specify a path to a specific .ipx file using:
The following example shows how you can integrate multiple DSP Builder designs
into a top-level Quartus II project. Suppose your top-level design consists of the
following three DSP Builder models:
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■
■
In the top-level Quartus II project, there are the following four design files:
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■
■
■
Figure 12–2 on page 12–7
Navigator window.
In this example, fir2.qip has an embedded .qip associated with the HDL import block
and fir3.qip has an embedded .qip associated with the IP MegaCore function block.
To update the IP Librarian search path, create additional directories <project
directory>/ip/<module name> and create an .ipx file in each subdirectory.
Thus in this design example, create the following directories:
■
■
■
and in each subdirectory, create a text file <module name>.ipx with the following
contents:
<library>
<path path='../../../<module name1>/**/*'/>
<path path='../../../<module name2>/**/*'/>
...
</library>
<index file='../../../blockdemo.ipx'/>
fir1.mdl—containing two Avalon-MM slave interfaces
fir2.mdl—containing multiple HDL import blocks
fir3.mdl—containing one IP MegaCore function block with two Avalon-ST
interfaces
top.vhd—Top-level wrapper that instantiates the three separate models
fir1.qip—Quartus IP file for fir1.mdl
fir2.qip—Quartus IP file for fir2.mdl
fir3.qip—Quartus IP file for fir3.mdl
../<project directory>/ip/fir1
../<project directory>/ip/fir2
../<project directory>/ip/fir3
<library>
<path path='../../../<module name>/**/*'/>
shows the design example in the Quartus II Project
Preliminary
Integration of Multiple Models in a Top-Level Quartus II Project
© June 2010 Altera Corporation
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