IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 69
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 69 of 422
- Download datasheet (6Mb)
Chapter 3: Design Rules and Procedures
Analyzing the Hardware Resource Usage
Analyzing the Hardware Resource Usage
© June 2010 Altera Corporation
You can use the alt_dspbuilder_refresh_hdlimport command to update
these blocks. This command checks that the referenced HDL files (or Quartus II
project) exists. If it finds the references, the HDL Import dialog box opens and a
compilation is automatically invokes to regenerate the Simulink model. If it finds
neither, but there is an existing simulation netlist, it uses this netlist for simulation.
To run the command, follow these steps:
1. Start the MATLAB or Simulink software.
2. Open a Simulink model that contains imported HDL.
3. Run the command by typing the following at the MATLAB prompt:
You can optionally select a HDL Import block to run the command on only the
selected subsystem.
To analyze the hardware resources required for your design with a Resource Usage
block, follow these steps:
1. Select the AltLab library from the Altera DSP Builder BlockSet folder in the
2. Drag and drop a Resource Usage block into your model and double-click on
3. Double-click on the Signal Compiler block and click Compile to recompile
Figure 3–23. Resource Usage Block
alt_dspbuilder_refresh_hdlimport r
Simulink Library Browser.
the block to open the Resource Usage dialog box.
your design in the Quartus II software.
The Resource Usage block updates to show a summary of the estimated logic,
RAM and DSP block usage
The Resource Usage dialog box updates to show a detailed report of the resources
that each of the blocks require in your model that generate hardware.
Preliminary
(Figure
3–23).
DSP Builder Standard Blockset User Guide
3–25
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: