IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 347

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Dual-Port RAM
Dual-Port RAM
© June 2010 Altera Corporation
f
f
1
The Dual-Port RAM block maps data to an embedded RAM (embedded array block,
EAB; or embedded system block, ESB) in Altera devices. The read and write ports are
separate.
The Dual-Port RAM block accepts any data type as input. The input port always
registers and the output port can optionally be registered.
The input address bus must be unsigned. The clock enable signal (ena) bypasses any
output register.
Turning on DONT_CARE may give a higher f
memory implements as a MLAB. When this option is on, the output is not
double-registered (and therefore, in the case of MLAB implementation, uses fewer
external registers), and you gain an extra half-cycle on the output. The default is off,
which outputs old data for read-during-write.
For more information about this option, refer to the Read-During-Write Output Behavior
section in the
The contents of the RAM are pre-initialized to zero by default. Use an Intel
Hexadecimal (.hex) file or MATLAB array to specify them. Use the Quartus II
software to generate a.hex file that must be in your DSP Builder working directory.
The data in a standard .hex file is formatted in multiples of eight and the output bit
width should also be in multiples of eight. The Quartus II software does allow you to
create non-standard .hex files but pads 1's to the front for negative numbers to make
them multiples of eight. Thus, large numbers with less bits may be treated as negative
numbers. A warning issues if you specify a non-standard .hex file. If you require a
different bit width, you should set the output bit width to the same as that in the .hex
file but use an
supports 32-bit addressing with extended linear address records in the .hex file.
For instructions on creating this file, refer to Creating a Memory Initialization File or
Hexadecimal (Intel-Format) File in the Quartus II Help.
The MATLAB array parameter must be a one dimensional MATLAB array with a
length less than or equal to the number of words. Specify the array from the MATLAB
workspace or directly in the MATLAB Array box.
Table 9–10
Table 9–10. Dual-Port RAM Block Inputs and Outputs
d
rd_add
wr_add
wren
ena
q_a
Signal
shows the Dual-Port RAM block inputs and outputs.
RAM Megafunction User Guide.
AltBus
Input
Input
Input
Input
Input
Output
Direction
block to convert to the required bit width. DSP Builder
Preliminary
Input data port.
Read address bus.
Write address bus.
Write enable.
Optional clock enable port
Output data port.
MAX
for your design, especially if the
Description
DSP Builder Standard Blockset Libraries
9–7