IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 298

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–12
Figure 5–9. Avalon-MM Write FIFO Content
Avalon Streaming Blocks
Avalon-ST Packet Format Converter
DSP Builder Standard Blockset Libraries
f
1
Figure 5–9
The Avalon Streaming blocks automate the process of specifying ports that are
compatible with an Avalon-ST interface. The blocks include an
Format
For information about the Avalon-ST interface, refer to the
Specifications.
The Avalon-ST Packet Format Converter (PFC) block transforms packets
received from one block to a different packet format required by another block.
The PFC takes packet data from one or more input interfaces, and provides field
reassignment in time and space to one or more output packet interfaces. You specify
the input packet format and the desired output packet format, then the appropriate
control logic automatically generates.
The PFC operates on a single clock domain, and supports multicast data, where an
input field is broadcast copied to multiple output fields. The ready latency of the PFC
block is zero and it can only connect to other Avalon-ST interfaces with a ready
latency of zero.
Verilog HDL generates for the PFC block and you must therefore have a license that
supports Verilog HDL when simulating in ModelSim.
Converter,
shows the content of the Avalon-MM Write FIFO block.
Avalon-ST Sink
Preliminary
and
Avalon-ST
Avalon Interface
Avalon-ST Packet Format Converter
Source.
© June 2010 Altera Corporation
Avalon-ST Packet
Chapter 5: Interfaces Library