IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 344

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–4
Table 9–6. Down Sampling Block I/O Formats
Figure 9–2. Down Sampling Block Example
Dual-Clock FIFO
Table 9–7. Dual-Clock FIFO Block Inputs and Outputs (Part 1 of 2)
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
d
wrreq
rdreq
aclr
q
rdfull
rdempty
rdusedw
I/O
Signal
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
[L1].[R1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
Input
Input
Input
Input
Output
Output
Output
Output
9–6:
Direction
1
Table 9–6
Figure 9–2
The Dual-Clock FIFO block implements a parameterized, dual-clock FIFO buffer
controlled by separate read-side and write-side clocks.
The Dual-Clock FIFO block simulation in Simulink is functionally equivalent to
hardware, but not cycle-accurate.
Table 9–7
(3)
[L].[R]
Data input to the FIFO buffer.
Write request control. The d[] port is written to the FIFO buffer.
Read request control. The oldest data in the FIFO buffer goes to the q[] port.
Optional asynchronous clear input, which flushes the FIFO.
Data output from the FIFO buffer.
Optional output synchronized to the read clock. Indicates that the FIFO buffer is full and
disables the wrreq port.
Optional output synchronized to the read clock. Indicates that the FIFO buffer is empty and
disables the rdreq port.
Optional output synchronized to the read clock. Indicates the number of words that are in the
FIFO buffer.
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Down Sampling block I/O formats.
shows the Dual-Clock FIFO block inputs and outputs.
shows an example with the Down Sampling block.
(Note 1)
Preliminary
Description
VHDL
© June 2010 Altera Corporation
Chapter 9: Storage Library
Dual-Clock FIFO
Type
Implicit
Implicit
(4)