IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 271
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
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Chapter 4: Gate & Control Library
Demultiplexer
Table 4–14. Demultiplexer Block Parameters
Table 4–15. Demultiplexer Block I/O Formats
Figure 4–5. Demultiplexer Block Example
© June 2010 Altera Corporation
Number of Output Data Lines An integer greater than 1
Use Enable Port
Use Synchronous Clear Port
I
O
Notes to
(1) Where I is the number of outputs to the demultiplexer.
(2) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(3) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(4) I1
(5) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
...
On
[L].[R]
[L].[R]
[L].[R]
[1]
[1]
[L].[R]
[L].[R]
Table
Simulink (3),
is an input port. O1
Name
(1)
4–15:
Table 4–14
Table 4–15
Figure 4–5
(4)
[L].[R]
is an output port.
(Parameterizable)
On or Off
On or Off
I1: in STD_LOGIC_VECTOR({L + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
...
On: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
describes the parameters for the Demultiplexer block.
shows the Demultiplexer block I/O formats.
shows an example with the Demultiplexer block.
Value
(Note 2)
Preliminary
Specify how many outputs you want the demultiplexer to have.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
Implicit
Implicit
Implicit
(5)
4–9
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