IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 29
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 29 of 422
- Download datasheet (6Mb)
Chapter 2: Getting Started
Creating the Amplitude Modulation Model
Add the Delay Block
© June 2010 Altera Corporation
3. Drag and drop the Input block from the Simulink Library Browser into your
4. Click the text under the block icon in your model. Delete the text Input and type
5. Double-click the SinIn block in your model to display the Block Parameters
6. Set the SinIn block parameters
Table 2–2. Parameters for the SinIn Block
7. Click OK.
8. Draw a connection line from the right side of the Sine Wave block to the left side
To add the Delay block, follow these steps:
1. Select the Storage library from the Altera DSP Builder Blockset folder in the
2. Drag and drop the Delay block into your model and position it to the right of the
3. Double-click the Delay block in your model to display the Block Parameters
4. Type 1 as the Number of Pipeline Stages for the Delay block.
Parameter
Bus Type
[number of bits].[]
Specify Clock
model. Position the block to the right of the Sine Wave block.
If you are unsure how to position the blocks or draw connection lines, refer to the
completed design
1
the text SinIn to change the name of the block instance.
dialog box.
of the SinIn block by holding down the left mouse button and dragging the
cursor between the blocks.
1
Simulink Library Browser.
SinIn block.
dialog box
You can use the Up, Down, Right, and Left arrow keys to adjust the position
of a block.
Alternatively, you can select a block, hold down the Ctrl key and click the
destination block to automatically make a connection between the two
blocks.
(Figure
(Figure 2–7 on page
2–5).
Preliminary
(Table
2–14).
2–2).
Value
Signed Integer
16
Off
DSP Builder Standard Blockset User Guide
2–7
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: