MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 159

IC MCU 8K FLASH 8MHZ PWM 32-LQFP

MCHC908MR8VFAE

Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908MR8VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Part Number:
MCHC908MR8VFAE
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9.6.4 Output Port Control Register
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Conditions may arise in which the PWM pins need to be individually
controlled. This is made possible by the PWM output control register
(PWMOUT) shown in
If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx
bits. These bits behave according to
When OUTCTL is set, the polarity options TOPPOL and BOTPOL will
still affect the outputs. In addition, if complementary operation is in use,
the PWM pairs will not be allowed to be active simultaneously, and
dead-time will still not be violated. When OUTCTL is set and
Reset:
dress:
Read:
Write:
OUTx Bit
Pulse-Width Modulator for Motor Control (PWMMC)
Ad-
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Figure 9-18. PWM Output Control Register (PWMOUT)
$0025
BIt 7
0
0
1 — PWM1 is active.
0 — PWM1 is inactive.
1 — PWM2 is complement of PWM1.
0 — PWM2 is inactive.
1 — PWM3 is active.
0 — PWM3 is inactive.
1 — PWM4 is complement of PWM3.
0 — PWM4 is inactive.
1 — PWM5 is active.
0 — PWM5 is inactive.
1 — PWM6 is complement of PWM5.
0 — PWM6 is inactive.
ed
= Unimplement-
OUT-
CTL
6
0
Complementary Mode
Figure
OUT6
Table 9-4. OUTx Bits
5
0
Pulse-Width Modulator for Motor Control (PWMMC)
9-18.
OUT5
4
0
Table
OUT4
3
0
9-4.
OUT3
1 — PWM1 is active
0 — PWM1 is inactive
1 — PWM2 is active
0 — PWM2 is inactive
1 — PWM3 is active
0 — PWM3 is inactive
1 — PWM4 is active
0 — PWM4 is inactive
1 — PWM5 is active
0 — PWM5 is inactive
1 — PWM6 is active
0 — PWM6 is inactive
2
0
Independent Mode
OUT2
1
0
Technical Data
Output Control
OUT1
Bit 0
0
159

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