MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 81

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
BNE rel
BPL rel
BRA rel
BRCLR n,opr,rel
BRN rel
BRSET n,opr,rel
BSET n,opr
BSR rel
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
CLI
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Source
Form
Branch if Not Equal
Branch if Plus
Branch Always
Branch if Bit n in M Clear
Branch Never
Branch if Bit n in M Set
Set Bit n in M
Branch to Subroutine
Compare and Branch if Equal
Clear Carry Bit
Clear Interrupt Mask
Clear
Operation
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Central Processor Unit (CPU)
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 3 + rel ? (Mn) = 1
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
PC ¨ (PC) + 2 + rel
PC ← (PC) + rel
PC ← (PC) + 2
SP ← (SP) – 1
Description
M ← $00
M ← $00
H ← $00
M ← $00
M ← $00
A ← $00
X ← $00
Mn ← 1
C ← 0
I ← 0
V H I N Z C
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – –
– – – – – – REL
– – – – –
– – – – – –
– – – – – – REL
– – – – – –
– – – – – 0 INH
– – 0 – – – INH
0 – – 0 1 –
Effect on CCR
Central Processor Unit (CPU)
Instruction Set Summary
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
Technical Data
9E6F
9E61
0D
0C
1C
AD rr
8C
26
2A
20
01
03
05
07
09
0B
0F
21
00
02
04
06
08
0A
0E
10
12
14
16
18
1A
1E
31
41
51
61
71
98
9A
3F
4F
5F
6F
7F
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
81
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
5
4
4
5
4
6
1
2
3
1
1
1
3
2
4