MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 69

IC MCU 8K FLASH 8MHZ PWM 32-LQFP

MCHC908MR8VFAE

Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908MR8VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
TOPNEG — Top-Side PWM Polarity Bit
INDEP — Independent Mode Enable Bit
LVIPWR — LVI Power Enable Bit
LVIRST — LVI Reset Enable Bit
STOPE — STOP Enable Bit
COPD — COP Disable Bit
TOPNEG determines if the top-side PWMs will have positive or
negative polarity. See
Control
INDEP determines if the motor control PWMs will be six independent
PWMs or three complementary PWM pairs. See
Pulse-Width Modulator for Motor Control
LVIPWR enables the LVI module. See
Inhibit
LVIRST enables the reset signal from the LVI module. See
Section 17. Low-Voltage Inhibit
STOPE enables the STOP instruction. See
Processor Unit
COPD disables the COP module. See
Operating Properly
1 = Negative polarity
0 = Positive polarity
1 = Six independent PWMs
0 = Three complementary PWM pairs
1 = LVI module power enabled
0 = LVI module power disabled
1 = LVI module resets enabled
0 = LVI module resets disabled
1 = STOP instruction is enabled.
0 = STOP instruction is disabled and executes as an illegal
1 = COP module disabled
0 = COP module enabled
instruction.
Configuration Register (CONFIG)
(LVI).
(PWMMC).
(CPU).
(COP).
Section 9. Pulse-Width Modulator for Motor
(LVI).
Section 15. Computer
Section 17. Low-Voltage
Configuration Register (CONFIG)
Section 6. Central
(PWMMC).
Section 9.
Technical Data
CONFIG Bits
69

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