MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 49

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Note 1. Writing a logic 0 clears SBSW.
U = Unaffected
nate
$FE0C
$FE0D
$FE00
$FE01
$FE03
$FE08
$FE0A
$FE0B
$FE0E
$005F
Addr.
SIM Break Status Regis-
SIM Reset Status Regis-
FLASH Control Register
Break Address Register
Break Address Register
trol Register (BRKSCR)
SIM Break Flag Control
Break Status and Con-
Register (SBFCR)
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 10)
See page 336.
See page 108.
See page 109.
See page 334.
See page 334.
See page 333.
X = Indetermi-
See page 57.
High (BRKH)
Low (BRKL)
Reserved
Reserved
(SRSR)
(SBSR)
(FLCR)
ter
ter
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read: POR
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
BCFE
BRKE
Bit 15
Bit 7
Bit 7
R
R
R
R
0
R
1
0
0
0
0
0
= Reserved
BRKA
Bit 14
Bit 6
PIN
Memory Map
R
R
R
R
R
6
0
0
0
0
0
0
Bit 13
COP
Bit 5
R
R
R
R
R
5
0
0
0
0
0
0
0
Bit 12
ILOP
Bold
Bit 4
Unimplemented
R
R
R
R
R
4
0
0
0
0
0
0
0
ered
= Buff-
HVEN
Bit 11
ILAD
Bit 3
R
R
R
R
R
3
0
0
0
0
0
0
MASS
Bit 10
Bit 2
R
R
R
R
R
2
0
0
0
0
0
0
0
= Unimplemented
ERASE
Note
SBSW
Bit 9
Bit 1
LVI
Technical Data
R
R
R
R
1
0
0
0
0
0
0
0
Memory Map
(1)
I/O Section
PGM
Bit 0
Bit 8
Bit 0
R
R
R
R
R
0
0
0
0
0
0
0
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