MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 368

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
synchronous — Refers to logic circuits and operations that are synchronized by a common
system integration module (SIM) — One of a number of modules that handle a variety of
TIM — See timer interface module (TIM).
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
two’s complement — A means of performing binary subtraction using addition techniques. The
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
V — The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
Technical Data
368
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch to
subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow
of the main program to execute the instructions in the subroutine. When the RTS instruction
is executed, the CPU returns to the main program where it left off.
reference signal.
control functions in the modular M68HC08 Family. The SIM controls mode of operation,
resets and interrupts, and system clock distribution.
frequency. Also see acquisition mode.
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and
BLT use the overflow bit.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor