MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 285

IC MCU 8K FLASH 8MHZ PWM 32-LQFP

MCHC908MR8VFAE

Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908MR8VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Price
Part Number:
MCHC908MR8VFAE
Manufacturer:
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Quantity:
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Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
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14.4.2 Data Direction Register B
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
DDRB[6:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 14-7
Reset:
dress:
Read:
Write:
Ad-
These read/write bits control port B data direction. Reset clears
DDRB[6:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
$0005
Bit 7
0
Figure 14-6. Data Direction Register B (DDRB)
shows the port B I/O logic.
Input/Output (I/O) Ports
= Unimplemented
DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
6
0
5
0
4
0
3
0
2
0
Input/Output (I/O) Ports
1
0
Technical Data
Bit 0
Port B
0
285

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