MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 98

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
7.4.2.3 Illegal Opcode Reset
7.4.2.4 Illegal Address Reset
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
Technical Data
98
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
Because the MC68HC08MR8 has stop mode disabled by bit 1 in the
CONFIG register, execution of the STOP instruction will cause an illegal
opcode reset if stop mode has not been enabled by setting CONFIG
register bit 1.
An opcode fetch from addresses other than FLASH, I/O, or RAM
addresses generates an illegal address reset (unimplemented locations
within memory map). The SIM verifies that the CPU is fetching an
opcode prior to asserting the ILAD bit in the SIM reset status register
(SRSR) and resetting the MCU. A data fetch from an unmapped address
does not generate a reset.
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
level for at least nine consecutive CPU cycles. The LVI bit in the SIM
reset status register (SRSR) is set, and the external reset pin (RST) is
held low while the SIM counter counts out 4096 CGMXCLK cycles.
Sixty-four CGMXCLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
DD
voltage falls to the LVI
System Integration Module (SIM)
LVRX
voltage and remains at or below that
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor