MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 336

IC MCU 8K FLASH 8MHZ PWM 32-LQFP

MCHC908MR8VFAE

Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908MR8VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Manufacturer
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Price
Part Number:
MCHC908MR8VFAE
Manufacturer:
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Quantity:
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Part Number:
MCHC908MR8VFAE
Manufacturer:
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Quantity:
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Break (BRK)
20.6.3 SIM Break Status Register
Technical Data
336
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Reset:
BW — Break Wait Bit
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The example
code shown in
break interrupt routine. Execute this code at the end of the break
interrupt routine.
dress:
Read:
Write:
Ad-
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
Note: Writing a logic 0
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
$FE00
Bit 7
R
0
0
Figure 20-6. SIM Break Status Register (SBSR)
clears BW.
Figure 20-7
R
6
0
0
Break (BRK)
R
R
5
0
0
works if the H register was stacked in the
= Reserved
R
4
1
1
R
3
0
0
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
R
2
0
0
Note
BW
1
0
Bit 0
R
0
0

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