MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 177

• Manufacturer Part Number: MCHC908MR8VFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.12.5 PWM Control Register 2
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
NOTE:
NOTE:
A PWM CPU interrupt request can still be generated when LDOK is 0.
PWM control register 2 controls the PWM load frequency, the PWM
correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
The user should initialize this register before enabling the PWM.
LDFQ1 and LDFQ0 — PWM Load Frequency Bits
When reading these bits, the value read is the buffer value (not
necessarily the value the PWM generator is currently using).
Reset:
dress:
Read:
Write:
Pulse-Width Modulator for Motor Control (PWMMC)
Ad-
These buffered read/write bits select the PWM CPU load frequency
according to
LDFQ1
$0021
Bit 7
0
Figure 9-36. PWM Control Register 2 (PCTL2)
Reload Frequency Bits
LDFQ1:LDFQ0
ed
LDFQ0
= Unimplement-
Table
Table 9-5. PWM Reload Frequency
6
0
00
01
10
11
9-5.
5
0
0
Pulse-Width Modulator for Motor Control (PWMMC)
SEL12
Bold
4
0
= Buffered
SEL34
PWM Reload Frequency
3
0
Every 2 PWM cycles
Every 4 PWM cycles
Every 8 PWM cycles
Every PWM cycle
SEL56
2
0
Control Logic Block
PRSC1 PRSC0
1
0
Technical Data
Bit 0
0
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