MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 222

IC MCU 8K FLASH 8MHZ PWM 32-LQFP

MCHC908MR8VFAE

Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908MR8VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Timer Interface A (TIMA)
11.10.5 TIMA Channel Registers
Technical Data
222
Register Name and Address:
Register Name and Address:
Register Name and Address:
Register Name and Address:
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 11-9. TIMA Channel Registers (TACH0H/L–TACH1H/L)
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Timer Interface A (TIMA)
Bit 14
Bit 14
Bit 6
Bit 6
6
6
6
6
Bit 13
Bit 13
Bit 5
Bit 5
5
5
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Bit 12
Bit 12
Bit 4
Bit 4
4
4
4
4
TACH0H — $0014
TACH1H — $0017
TACH0L — $0015
TACH1L — $0018
Bit 11
Bit 11
Bit 3
Bit 3
3
3
3
3
MC68HC908MR8 — Rev 4.1
Bit 10
Bit 10
Bit 2
Bit 2
Freescale Semiconductor
2
2
2
2
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
1
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0

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