HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1179

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
33.2.8
BBRB is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or
I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size as the break
conditions of channel B.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15 to 10 ⎯
9
8
7
6
5
4
Break Bus Cycle Register B (BBRB)
Bit Name
XYE
XYS
CDB1
CDB0
IDB1
IDB0
Initial
Value
All 0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits are always read as 0. The write value
should always be 0.
channel B break condition. Note that this bit setting is
enabled only when the L bus is selected in the CDB1
and CDB0 bits. Selection between the X memory bus
and Y memory bus is done by the XYS bit.
0: Selects L bus for the channel B break condition
1: Selects X/Y memory bus for the channel B break
channel B break condition.
0: Selects the X bus for the channel B break condition
1: Selects the Y bus for the channel B break condition
L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
Reserved
Selects the X memory bus or Y memory bus as the
Selects the X bus or the Y bus as the bus of the
condition
data access cycle
Section 33 User Break Controller (UBC)
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