HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1461

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Item
20.5 Interrupt Request
21.1 Features
21.3.1 Mode Register (SIMDR)
22.4.1 Interrupt Timing
(4) Interrupt Generator Circuit
Figure 22.4 Interrupt Generator
26.3.1 LCDC Input Clock
Register (LDICKR)
749
867
676
679
685
Page Revision (See Manual for Details)
Description added
There are six interrupt requests in this module; transmit
data empty, transmit end, receive data full, NACK
receive, STOP recognition, and arbitration lost/overrun
error. Table 20.3 shows the contents of each interrupt
request.
A common interrupt vector (IICI) is assigned to each
interrupt source.
Description amended
•
Table amended
Description amended
Interrupt is generated as is shown in figure 22.4. That
is, AFEIFI signal is generated by performing OR
operation on the four signals from ASTR1 in FIFO
interrupt control and the two signals from ASTR2 in
DAA interrupt control, and then sent out to INTC as one
interrupt signal (AFECI).
Figure amended
ASTR1
(FIFO control)
ASTR2
(DAA control)
Description amended
For a TFT panel, LCD_CL2 = DOTCLK, and for an STN
or DSTN monochrome panel, LCD_CL2 = a clock with a
frequency of (DOTCLK/data bus width of output to LCD
panel). For a color panel, LCD_CL2 = a clock with a
frequency of (3 × DOTCLK/data bus width of output to
LCD panel). The LDICKR must be set so that the clock
input to the LCDC is 66 MHz or less regardless of the
LCD_CL2.
Bit
4
Interrupts: One type (SIOFIn (n = 0, 1))
Bit Name
SYNCDL
Interrupt mask Interrupt factor
Interrupt mask Interrupt factor
2
4
Initial
Value
0
R/W
R/W
4
2
Description
Data Pin Bit Delay for SIOFSYNC Pin
Valid when the SIOFSYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission or reception in slave mode.
0: No bit delay
1: 1-bit delay
4
2
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AFECI