HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 268

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Cache
(2)
In write-back mode, an external write cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced is shown in table 5.4. When the U bit of the entry which is to be
replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to
the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The
LRU is updated to indicate that the replaced way is the most recently updated way. After the cache
has completed its update cycle, the write-back buffer writes the entry back to the memory.
Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the
write is only to the external memory.
5.3.5
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 5.3 shows the configuration of the write-back buffer.
5.3.6
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
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Write Miss
Write-Back Buffer
Coherency of Cache and External Memory
PA (31 to 4):
Longword 0 to 3:
PA (31 to 4)
Figure 5.3 Write-Back Buffer Configuration
Longword 0 Longword 1 Longword 2 Longword 3
Physical address written to external memory
One line of cache data to be written to external
memory
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010