HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 198
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 3 DSP Operating Unit
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from –32 to
+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
2. Negative Value Mode: CS[2:0] = B'001
3. Zero Value Mode: CS[2:0] = B'010
4. Overflow Mode: CS[2:0] = B'011
5. Signed Greater Than Mode: CS[2:0] = B'100
6. Signed Greater Than or Equal Mode: CS[2:0] = B'101
Page 138 of 1414
The DC bit indicates the last shifted out data as the operation result.
The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the
operation result is zero or a positive value.
The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is set to 1 when an overflow occurs.
The DC bit is always cleared to 0.
The DC bit is always cleared to 0.
base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard-
bit parts when a register not providing the guard-bit parts is specified as the source
operand. When a register not providing the guard-bit parts is specified as a destination
operand, the lower 32 bits of the operation result are input into the destination register.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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