HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 53

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 X/Y Memory
Table 6.1
Table 6.2
Section 7 Exception Handling
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Section 8 Interrupt Controller (INTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Table 9.12
Table 9.13
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
X/Y Memory Virtual Addresses ........................................................................... 213
MMU and Cache Settings..................................................................................... 216
Exception Event Vectors....................................................................................... 225
Instruction Positions and Restriction Types.......................................................... 235
SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
(SR.RC[11:0]≥2)................................................................................................... 237
Exception Acceptance in the Repeat Loop ........................................................... 239
Instruction Where a Specific Exception Occurs
When a Memory Access Exception Occurs in Repeat Control
(SR.RC[11:0]≥1)................................................................................................... 240
Pin Configuration.................................................................................................. 245
Interrupt Sources and IPRA to IPRJ ..................................................................... 248
Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 270
Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 272
Interrupt Level and INTEVT Code....................................................................... 275
Pin Configuration.................................................................................................. 283
Address Space Map 1 (CMNCR.MAP = 0).......................................................... 287
Address Space Map 2 (CMNCR.MAP = 1).......................................................... 288
Correspondence between External Pins (MD3 and MD4),
Memory Type of CS0, and Memory Bus Width................................................... 289
Correspondence between External Pin (MD5) and Endians................................. 289
32-Bit External Device/Big Endian Access and Data Alignment......................... 331
16-Bit External Device/Big Endian Access and Data Alignment......................... 332
8-Bit External Device/Big Endian Access and Data Alignment........................... 333
32-Bit External Device/Little Endian Access and Data Alignment ...................... 334
16-Bit External Device/Little Endian Access and Data Alignment ...................... 335
8-Bit External Device/Little Endian Access and Data Alignment ........................ 336
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (1)-1..................................................................... 349
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (1)-2..................................................................... 350
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (2)-1..................................................................... 351
Page liii of lx