HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 720

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 I
20.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and
when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF.
20.3.8
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is
H'FF.
20.3.9
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
20.3.10 I
ICCKS is enabled in master mode and selects a transfer clock used in master mode. Specify
ICCKS according to the required transfer rate. For transfer rate, see table 20.2.
Page 660 of 1414
Bit
7 to 5
4
3
2
1
0
I
I
I
2
C Bus Interface (IIC)
Bit Name
⎯
CKS4
CKS3
CKS2
CKS1
CKS0
2
2
2
2
C Bus Transmit Data Register (ICDRT)
C Bus Receive Data Register (ICDRR)
C Bus Shift Register (ICDRS)
C Bus Master Transfer Clock Select Register (ICCKS)
Initial
Value
All 0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1. The write value
should always be 0.
Master Transfer Clock Select 4 to 0
Specify these bits according to the required
transfer rate in master mode. In slave mode, these
bits are used to ensure the data setup time in
transmit mode.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010