HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 288

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Exception Handling
• Save address
• Exception code
• Remarks
(2)
• Conditions
Note: For details on undefined code, refer to table 2.12. When an undefined code other than
• Types
• Save address
• Exception code
• Remarks
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Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'0E0
An exception occurred during write: H'100
The virtual address (32 bits) that caused the exception is set in TEA.
⎯ When undefined code not in a delay slot is decoded
⎯ When a privileged instruction not in a delay slot is decoded in user mode
Instruction synchronous, re-execution type
An instruction address where an exception occurs
H'180
None
Illegal general instruction exception
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
H'F000 to H'FFFF is decoded, operation cannot be guaranteed.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010