HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 685

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: Even when the receive error (framing error/parity error) is generated, receive operation is
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
Figure 18.9 shows an example of the operation for reception.
When modem control is enabled, transmission can be stopped and restarted in accordance with the
CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark
state after transmission of one frame. When CTS is set to 0, the next transmit data is output
starting from the start bit.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
interrupt request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive data ready
interrupt request is generated.
Note that a common vector is assigned to each interrupt source.
continued.
Serial
RDF
FER
data
1
Start
bit
0
Figure 18.9 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
D 0 D 1
One frame
Data
D 7
Receive-FIFO-data-full
Parity
interrupt request
bit
0/1
Stop
bit
1
receive-FIFO-data-ful
Data read and RDF
flag read as 1 then
interrupt handler
Start
cleared to 0 by
bit
0
Section 18 Serial Communication Interface with FIFO (SCIF)
D 0
D 1
Data
D 7 0/1
Receive-error interrupt
request generated
Parity
by receive error
bit
Stop
bit
1
(mark state)
Idle state
1
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