HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 724

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 I
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
(Master output)
Page 664 of 1414
(Master output)
(Slave output)
processing
ICDRT
ICDRS
TDRE
TEND
User
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
SDA
SDA
SCL
2
C Bus Interface (IIC)
[2] Instruction of start
condition issuance
Figure 20.5 Master Transmit Mode Operation Timing (1)
Bit 7
1
[3] Write data to ICDRT (first byte)
Bit 6
2
Address + R/W
Bit 5
3
Address + R/W
Slave address
Bit 4
4
Bit 3
5
Bit 2
6
[4] Write data to ICDRT (second byte)
Bit 1
7
Bit 0
R/W
8
A
9
SH7720 Group, SH7721 Group
[5] Write data to ICDRT (third byte)
R01UH0083EJ0400 Rev. 4.00
Data 1
Data 1
Bit 7
1
Bit 6
Data 2
2
Sep 21, 2010