HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 797

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
22.3.1
ACTR is the control register for AFEIF and is composed of ACTR1 and ACTR2. ACTR1 is
mainly used for FIFO control commands. ACTR2 is used for AFE control commands and DAA
control commands.
• ACTR1
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15
14 to 8
7
6, 5
4
3
2
AFEIF Control Register 1 and 2 (ACTR1, ACTR2)
HC
⎯
DLB
⎯
FFSZ2
FFSZ1
FFSZ0
Bit Name
Initial Value
0
All 0
0
All 0
0
0
0
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Description
AFE Hardware Control
This bit controls AFE. AFE_HC1 signal is made
to high directly often the next serial transmit data
transfer, when this bit is written to 1. Then ACDR
data (AFE control word) is transferred by
founding the second AFE.FS. AFEIF module
automatically makes AFE_HC1 signal to low and
HC bit to 0, directly after transferring the AFE
control word. See section 22.4.2, AFE Interface
for more detail about AFE control sequences.
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Digital Loop Back
0: Normal operation
1: Digital loop back between transmit FIFO and
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Interrupt Size Set 2 to 0
Specifies the size of FIFO. FIFO size to generate
interrupt (TFE, RFF, THE, and RHF) is assigned
as listed in table 22.2.
receive FIFO is performed. In this time the
transmit data is output to AFE_TXOUT, too.
Section 22 Analog Front End Interface (AFEIF)
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