HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 794

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 21 Serial I/O with FIFO (SIOF)
21.5
21.5.1
(1)
If SYNC signal output is enabled (FSE bit = 1), while output of the SYNC signal is disabled by
clearing the SICTR.FSE bit in master mode 2 to 0, the High period of the SYNC signal may more
quickly become 1 bit long with the rising edge of the SYNC signal in the head frame. However,
this period will not be generated after the second frame.
(2)
To avoid this problem, either counter-measure (a) or (b) is recommended.
(a)
(b)
Page 734 of 1414
SYNC
TXD
Problem
How to Avoid the Problem
When outputting data to the head frame, write dummy data to the transmission FIFO and
write valid data after the second frame. The data of the head frame should be read and
omitted at the receive side.
Use a configuration that does not occur malfunction, even if the period of the SYNC signal
becomes 1 bit longer than that of the value set in the head frame.
Usage Notes
Regarding SYNC Signal High Width when Restarting Transmission in Master
Mode 2
17 bit width
1 bit long
Figure 21.21 Frame Length (32-Bit)
32 bit (Valid data)
16 bit width
16 bit width
32 bit (Valid data)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
16 bit width
Sep 21, 2010