HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 750

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 21 Serial I/O with FIFO (SIOF)
21.3.4
SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the
receive FIFO and is initialized by the conditions specified in section 37, List of Registers, or by a
receive reset caused by the RXRST bit in SICTR.
Page 690 of 1414
Bit
31 to 16
15 to 0
Receive Data Register (SIRDR)
Bit Name
SIRDL
15 to 0
SIRDR
15 to 0
Initial
Value
All 0
All 0
R/W
R
R
Description
Left-Channel Receive Data
Store data received from the SIOFRxD pin as left-
channel data. The position of the left-channel data in
the receive frame is specified by the RDLA bit in
SIRDAR.
Right-Channel Receive Data
Store data received from the SIOFRxD pin as right-
channel data. The position of the right-channel data in
the receive frame is specified by the RDRA bit in
SIRDAR.
These bits are valid only when the RDLE bit in
SIRDAR is set to 1.
These bits are valid only when the RDRE bit in
SIRDAR is set to 1.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

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