MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1104

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC562/MPC564 Compression Features
A.3.2
The MPC562/MPC564 uses DECRAM for decompressor vocabulary tables (VT1 and VT2) storage in
decompression on mode. The ICDU utilizes DECRAM as two separately accessed 1-Kbyte RAM arrays
(16 bits wide) that are accessed via internal ICDU buses. The VTs should be loaded before the
decompression process starts. In order to allow decompression, the DECRAM must be disabled for the
U-bus accesses after VTs and decompressor class configuration registers (DCCRs) are initialized.
A.3.3
Setting BBCMCR[DECOMP_SC_EN] when decompression is enabled allows READI to track the
compressed code (see
if there is no intention to use compressed code, as it will degrade U-bus performance. The show cycle may
be delayed by one clock by the USIU if the show cycle occurs after an external device read cycle. Refer
to
The ICTRL register must be programmed such that a show cycle will be performed for all changes in the
program flow (ISCTL field = 0b01), or the PTM bit must be set and ISCTL must be set to a value other
than 0b11. (See
A.3.3.1
A-16
Section 24.6.5.2, “Compressed Code Mode
1
Reset
Reset
Field
Field IWP2
Addr
Changing the instruction show cycle programming starts to take effect only from the second instruction after the
actual mtspr to ICTRL.
MSB
Vocabulary Table Storage Operation
READI Compression
16
0
I-Bus Support Control Register (ICTRL)
The BBCMCR[DECOMP_SC_EN] bit determines if the data portion
(DATA[0:4]) of the instruction show cycle is driven or not, regardless of
decompression mode (BBCMCR[EN_COMP] bit)
CTA
Table
17
1
IWP3
18
2
A-2.)
Chapter 24, “READI
19
3
SIWP0
Figure A-13. I-Bus Support Control Register (ICTRL)
EN
20
4
CTB
MPC561/MPC563 Reference Manual, Rev. 1.2
SIWP1
EN
21
5
SIWP2
EN
22
Module”). BBCMCR[DECOMP_SC_EN] should not be set
6
0000_0000_0000_0000
0000_0000_0000_0000
Guidelines.”
SIWP3
NOTE
CTC
EN
23
7
SPR 158
DIWP0
EN
24
8
DIWP1
EN
25
9
DIWP2
CTD
EN
10
26
DIWP3
EN
11
27
IFM ISCT_SER
Freescale Semiconductor
12
28
IWP0
13
29
14
30
IWP1
LSB
15
31
1