MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 504

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
last sub-queue (after the queue completion flag is set), causes the execution to continue with the first
sub-queue, starting with the first CCW in the queue.
When the QADC64E encounters a CCW with the pause bit set, the queue enters the paused state after
completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause
software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating
completion of a sub-queue. The QADC64E then waits for another trigger event to again begin execution
of the next sub-queue.
13.5.3
The following are queue operation boundary conditions:
Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit
is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW
with the pause bit set completes normally. The pause flag is set. However, since the end-of-queue condition
is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
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The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code. The queue becomes
active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and
the queue becomes idle. A conversion is not performed.
BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on
queue 2. Refer to
The end-of-queue condition is recognized, a conversion is performed, the completion flag is set,
and the queue becomes idle.
BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0, the end-of-queue
condition is recognized, the completion flag is set, and the queue becomes idle. A conversion is not
performed.
BQ2 is set beyond the end of the CCW table (64 – 127) and a trigger event occurs on queue 2. The
end-of-queue condition is recognized immediately, the completion flag is set, and the queue
becomes idle. A conversion is not performed.
The pause bit is set in CCW5 and the EOQ code is in CCW6
The pause is set in CCW63
During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21
Boundary Conditions
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64E behavior. For example, if BQ2
is set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs
on queue 1, the QADC64E reads CCW0 and detects both end-of-queue
conditions. The completion flag is set and queue 1 becomes idle.
Section 13.3.7, “Control Register 2
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
(QACR2),” for more information on BQ2.
Freescale Semiconductor