MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 798

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Modular Input/Output Subsystem (MIOS14)
17.12.3.2 Interrupt Enable Register (MIOS14ER0)
This register contains the interrupt enable bits for the submodules. Each bit corresponds to a given
submodule.
17.12.3.3 Interrupt Request Pending Register (MIOS14RPR0)
This register is a read only register that contains the interrupt pending bits for the submodules. Each bit
corresponds to a given submodule. When one of these bits is set, it means that a submodule raised its flag
and the corresponding enable was set.
17-66
SRESET
SRESET
10:15
10:15
Bits
Bits
0:4
5:6
7:9
0:4
5:6
7:9
Field EN15 EN14 EN13 EN12 EN11
Addr
Field FLG
Addr
FLG15:11 Flag Bits — MDASM flag bits [15:11]
MSB
EN15:11 Enable Bits — MDASM enable bits [15:11]
FLG8:6
FLG5:0
MSB
0
Name
Name
EN8:6
EN5:0
15
0
—
—
FLG
1
14
1
Reserved
Flag Bits — MMCSM flag bits [8:6]
Flag Bits — PWMSM flag bits [5:0]
Reserved
Enable Bits — MMCSM enable bits [8:6]
Enable Bits — PWMSM enable bits [5:0]
2
FLG
Figure 17-36. Interrupt Enable Register (MIOS14ER0)
Figure 17-35. Interrupt Status Register (MIOS14SR0)
13
2
3
Table 17-36. MIOS14ER0 Bit Descriptions
FLG
Table 17-35. MIOS14SR0 Bit Description
MPC561/MPC563 Reference Manual, Rev. 1.2
12
3
4
FLG
11
4
5
5
—
—
0000_0000_0000_0000
6
6
0x30 6C00
0x30 6C04
Undefined
EN8
FLG
7
8
7
Description
Description
EN7
FLG
8
7
8
EN6
FLG
9
6
9
FLG
EN5
10
10
5
FLG
EN4
11
11
4
FLG
EN3
12
3
12
Freescale Semiconductor
FLG
EN2
13
2
13
FLG
EN1
14
1
14
FLG
LSB
EN0
15
LSB
0
15