MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 346

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

External Bus Interface
9-6
Transfer acknowledge
Signal Name
Transfer error
acknowledge
DATA[0:31]
Data bus
TEA
TA
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Pins
32
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Active
High
Low
Low
Transfer Cycle Termination
I/O
Data
O
O
O
I
I
I
The data bus has the following byte lane assignments:
Data Byte
DATA[0:7]
DATA[8:15]
DATA[16:23]
DATA[24:31]
Driven by the MPC561/MPC563 when it owns the
external bus and it initiated a write transaction to a
slave device. For single beat transactions, the byte
lanes not selected for the transfer by ADDR[30:31]
and TSIZ[0:1] do not supply valid data.
In addition, the MPC561/MPC563 drives the
DATA[0:31] when an external master owns the
external bus and initiated a read transaction to an
internal slave module.
Driven by the slave in a read transaction. For single
beat transactions, the MPC561/MPC563 does not
sample byte lanes that are not selected for the transfer
by ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave module
drives DATA[0:31].
Driven by the slave device to which the current
transaction was addressed. Indicates that the slave
has received the data on the write cycle or returned
data on the read cycle. If the transaction is a burst, TA
should be asserted for each one of the transaction
beats.
Driven by the MPC561/MPC563 when the slave
device is controlled by the on-chip memory controller
or when an external master initiated a transaction to
an internal slave module.
Driven by the slave device to which the current
transaction was addressed. Indicates that an error
condition has occurred during the bus cycle.
Driven by the MPC561/MPC563 when the internal
bus monitor detected an erroneous bus condition, or
when an external master initiated a transaction to an
internal slave module and an internal error was
detected.
Byte Lane
0
1
2
3
Description
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