R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1039

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20.3.26 MC UV Padding Size Setting Register (MCUVPR)
MCUVPR is in the MC register block and sets the input UV padding size in byte units.
Notes: 1. Addition is performed taking that 1 pixel = 1 byte.
Initial value:
Initial value:
Bit
31 to 12 ⎯
11 to 0
R/W:
R/W:
BIt:
BIt:
2. MCWR (bytes)/2 + MCUVPR (bytes) should be 8 bytes x n (n: an integer greater than
3. MCWR (bytes)/2: Shifts the MCWR setting one bit to the right. (When the setting is odd,
Bit Name
MC_UVP
0)
the bit 0 setting is discarded.)
31
15
⎯
⎯
⎯
⎯
0
0
30
14
⎯
⎯
⎯
⎯
0
0
29
13
⎯
⎯
⎯
⎯
0
0
Initial
Value
All 0
All 0
28
⎯
⎯
12
⎯
⎯
0
0
R/W
R/W
⎯
R/W
27
⎯
⎯
11
0
0
R/W
26
10
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Input UV padding size setting
Should be set by the number of bytes.
R/W
25
⎯
⎯
0
9
0
R/W
24
⎯
⎯
0
8
0
20. Graphics Data Translation Accelerator (GDTA)
R/W
23
⎯
⎯
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1007 of 1658
R/W
22
⎯
⎯
0
6
0
MC_UVP
R/W
21
⎯
⎯
0
5
0
R/W
20
⎯
⎯
0
4
0
R/W
19
⎯
⎯
0
3
0
REJ09B0261-0100
R/W
18
⎯
⎯
0
2
0
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0