R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 337

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 10.7 Reflection time for INT2A0 and INT2A1 when Interrupt Source Bit in
Module
WDT, TMU, SCIF, HSPI, SIOF,
MMCIF, DU, SSI, HAC, FLCTL
H-UDI, GDTA
PCIC (excluding the pin input-
related interrupt sources
PCIINTA, PCIINTB, PCIINTC,
and PCIINTD)
Peripheral Module Is Set/Cleared
Relation between Setting/Clearing Interrupt Source of
Module and Indication by INT2A0 and INT2A1
When an interrupt source bit is set in the register* in the
module that indicates generation of interrupt requests, the
same interrupt status information is read from that register and
INT2A0 or INT2A1. This means that the time required for
reflection in INT2A0 and INT2A1 is guaranteed by hardware.
When an interrupt source is cleared, the status after the source
is cleared can be read from INT2A0 or INT2A1 if read after
clearing the interrupt source flag in the module.
When an interrupt source bit is set in the register* in the
module that indicates generation of interrupt requests (SDINT
in the H-UDI, GACISR in the GDTA), the same interrupt status
information is read from that register and INT2A0 or INT2A1.
This means that the time required for reflection in INT2A0 and
INT2A1 is guaranteed by hardware.
When an interrupt source is cleared, the time required for
reflection in INT2A0 and INT2A1 can be guaranteed by
dummy-reading SDINT in the H-UDI or GACISR in the GDTA
once after clearing the interrupt source flag in the module.
When a PCIC interrupt source bit is set in PCIIR, PCIAINT, or
PCIPINT that indicates generation of interrupt requests, the
time required for reflection in INT2A0 and INT2A1 is
guaranteed by dummy-reading an arbitrary register in the INTC
once and then reading from INT2A0 or INT2A1.
When a PCIC interrupt source is cleared, the time required for
reflection in INT2A0 and INT2A1 is guaranteed in this way:
after writing to PCIIR, PCIAINT, or PCIPINT, dummy-read
PCIIR, PCIAINT, or PCIPINT once and then dummy-read an
arbitrary register in the INTC.
Rev.1.00 Jan. 10, 2008 Page 305 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100