R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 702

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Notes: 1. To clear the flag, the HE and TE bits in CHCR can be read as 1, and then, 0 can be
Rev.1.00 Jan. 10, 2008 Page 670 of 1658
REJ09B0261-0100
Channel Name
6 to 11
10
11
6
7
8
9
6, 7
8, 9
10, 11
2. To clear the flag, the AE and NMIF bits in DMAOR can be read as 1, and then, 0 can be
3. Accessing with other access sizes is prohibited.
4. The synchronous clock for the HE and TE bits in CHCR is Bck, and the synchronous
5. The synchronous clock for the AE, NMIF, and DME bits in DMAOR is Bck, and the
DMA operation register 1
DMA source address register 10
DMA destination address register 10 DAR10
DMA transfer count register 10
DMA channel control register 10
DMA source address register 11
DMA destination address register 11 DAR11
DMA transfer count register 11
DMA channel control register 11
DMA source address register B6
DMA destination address register B6 DARB6
DMA transfer count register B6
DMA source address register B7
DMA destination address register B7 DARB7
DMA transfer count register B7
DMA source address register B8
DMA destination address register B8 DARB8
DMA transfer count register B8
DMA source address register B9
DMA destination address register B9 DARB9
DMA transfer count register B9
DMA extended resource selector 3
DMA extended resource selector 4
DMA extended resource selector 5
written to.
written to.
clock for the other bits in CHCR is Pck.
synchronous clock for the CMS and PR bits in DMAOR is Pck.
Abbrev.
DMAOR1
SAR10
TCR10
CHCR10
SAR11
TCR11
CHCR11
SARB6
TCRB6
SARB7
TCRB7
SARB8
TCRB8
SARB9
TCRB9
DMARS3
DMARS4
DMARS5
R/W
R/W*
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
1
P4 Address
H'FCC0 8060
H'FCC0 8070
H'FCC0 8074
H'FCC0 8078
H'FCC0 807C
H'FCC0 8080
H'FCC0 8084
H'FCC0 8088
H'FCC0 808C
H'FCC0 8120
H'FCC0 8124
H'FCC0 8128
H'FCC0 8130
H'FCC0 8134
H'FCC0 8138
H'FCC0 8140
H'FCC0 8144
H'FCC0 8148
H'FCC0 8150
H'FCC0 8154
H'FCC0 8158
H'FCC0 9000
H'FCC0 9004
H'FCC0 9008
Area 7
Address
H'1CC0 8060
H'1CC0 8070
H'1CC0 8074
H'1CC0 8078
H'1CC0 807C
H'1CC0 8080
H'1CC0 8084
H'1CC0 8088
H'1CC0 808C
H'1CC0 8120
H'1CC0 8124
H'1CC0 8128
H'1CC0 8130
H'1CC0 8134
H'1CC0 8138
H'1CC0 8140
H'1CC0 8144
H'1CC0 8148
H'1CC0 8150
H'1CC0 8154
H'1CC0 8158
H'1CC0 9000
H'1CC0 9004
H'1CC0 9008
Access
Size*
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
3
Sync
clock
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck, Pck*
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Bck
Pck
Pck
Pck
5
4
4