R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 28

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

26.4 Operation ......................................................................................................................... 1314
26.5 Usage Note....................................................................................................................... 1335
Section 27 NAND Flash Memory Controller (FLCTL)
27.1 Features............................................................................................................................ 1337
27.2 Input/Output Pins............................................................................................................. 1340
27.3 Register Descriptions....................................................................................................... 1342
27.4 Operation ......................................................................................................................... 1364
27.5 Example of Register Setting ............................................................................................ 1373
27.6 Interrupt Processing ......................................................................................................... 1376
27.7 DMA Transfer Settings.................................................................................................... 1376
Rev.1.00 Jan. 10, 2008 Page xxvi of xxx
REJ09B0261-0100
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.5.1
26.5.2
26.5.3
27.3.1
27.3.2
27.3.3
27.3.4
27.3.5
27.3.6
27.3.7
27.3.8
27.3.9
27.3.10 Ready Busy Timeout Counter (FLBSYCNT)................................................... 1360
27.3.11 Data FIFO Register (FLDTFIFO)..................................................................... 1361
27.3.12 Control Code FIFO Register (FLECFIFO)....................................................... 1362
27.3.13 Transfer Control Register (FLTRCR)............................................................... 1363
27.4.1
27.4.2
27.4.3
27.4.4
Bus Format ....................................................................................................... 1314
Non-Compressed Modes .................................................................................. 1315
Compressed Modes........................................................................................... 1324
Operation Modes .............................................................................................. 1327
Transmit Operation........................................................................................... 1328
Receive Operation ............................................................................................ 1331
Serial Clock Control ......................................................................................... 1334
Restrictions when an Overflow Occurs during Receive DMA Operation ........ 1335
Pin Function Setting for the SSI Module.......................................................... 1335
Usage Note in Slave Mode ............................................................................... 1335
Common Control Register (FLCMNCR) ......................................................... 1344
Command Control Register (FLCMDCR)........................................................ 1346
Command Code Register (FLCMCDR) ........................................................... 1348
Address Register (FLADR) .............................................................................. 1349
Address Register 2 (FLADR2) ......................................................................... 1351
Data Counter Register (FLDTCNTR) .............................................................. 1352
Data Register (FLDATAR) .............................................................................. 1353
Interrupt DMA Control Register (FLINTDMACR) ......................................... 1354
Ready Busy Timeout Setting Register (FLBSYTMR) ..................................... 1359
Operating Modes .............................................................................................. 1364
Command Access Mode ................................................................................... 1364
Sector Access Mode ......................................................................................... 1368
Status Read ....................................................................................................... 1371
.......................................... 1337