R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1148

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV

Manufacturer Part Number
R8A77850ADBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1116 of 1658
REJ09B0261-0100
Bit
3
2
Bit Name
TFOVF
TFUDF
Initial
Value
0
0
R/W
R/W
R/W
Transmit FIFO Overflow
Description
0: Indicates that no transmit FIFO overflow occurs
1: Indicates that a transmit FIFO overflow occurs
A transmit FIFO overflow means that there has been an
attempt to write to SITDR when the transmit FIFO is full.
When a transmit FIFO overflow occurs, the SIOF
indicates overflow, and writing is invalid.
Transmit FIFO Underflow
0: Indicates that no transmit FIFO underflow occurs
1: Indicates that a transmit FIFO underflow occurs
A transmit FIFO underflow means that loading for
transmission has occurred when the transmit FIFO is
empty.
When a transmit FIFO underflow occurs, the SIOF
repeatedly sends the previous transmit data.
This bit is valid when the TXE bit in SICTR is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
To enable the issuance of this interrupt source, set
the TFOVFE bit in SIIER to 1.
This bit is valid when the TXE bit in SICTR is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
To enable the issuance of this interrupt source, set
the TFUDFE bit to 1.

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