R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1538

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

30. User Debugging Interface (H-UDI)
30.4.3
The H-UDI is reset by a power-on reset by the SDIR command. To reset the H-UDI, send the H-
UDI reset assert command from the H-UDI pin, and then send the H-UDI reset negate command
(see figure 30.4). The time required between the H-UDI reset assert and H-UDI reset negate
commands is the same as the time to keep the reset pin low in order to reset this LSI by a power-
on reset. After the H-UDI reset assert command is set, the reset signal is asserted in the chip after
four cycles at a peripheral clock (Pck). When the H-UDI reset negate command is set, the reset
signal is negated in the chip after a reset hold period. (The minimum period is 17 cycles at a
peripheral clock, and the maximum period is 42 cycles at a peripheral clock. For details, see
section 15, Clock Pulse Generator (CPG).)
Note: The WDT/RST module is not initialized. However, the overflow counter of the WDT/RST
STATUS[1:0] output
Rev.1.00 Jan. 10, 2008 Page 1506 of 1658
REJ09B0261-0100
Reset in the chip
CPU state
module is initialized.
H-UDI pin
H-UDI Reset
reset asserted
LL (normal)
Normal
H-UDI
Figure 30.4 H-UDI Reset
Pck 4 cycles
Command set timing
reset negated
HH (reset)
Reset
H-UDI
Reset hold period
Reset processing
LL (normal)